View ISL70417SEHEVAL1Z_4605653.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 rad hard 40v quad precision low power operational amplifiers isl70417seh the isl70417seh contains four very high precision amplifiers featuring the perfect combination of low noise vs power consumption. low offset voltage, low i bias current and low temperature drift making them the ideal choice for applications requiring both high dc accuracy and ac performance. the combination of high precision, low noise, low power and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls, and industrial controls. the isl70417seh is offered in a 14 lead hermetic ceramic flatpack package. the device is offered in an industry standard pin configuration and operates over the extended temperature range from -55c to +125c. applications ? precision instrumentation ? spectral analysis equipment ? active filter blocks ? thermocouples and rtd reference buffers ? data acquisition ? power supply control features ? electrically screened to dla smd# 5962-12228 ? low input offset voltage . . . . . . . . . . . . . . . . . . 110v, max. ? superb offset temperature coefficient . . . . . . 1v/c, max. ? input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . 5na, max. ? input bias current tc . . . . . . . . . . . . . . . . . . . . 5pa/c, max. ? low current consumption . . . . . . . . . . . . . . . . . . . . . . . 440a ? voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nv/ hz ? wide supply range . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 40v ? operating temperature range. . . . . . . . . . .-55c to +125c ? radiation environment - sel/seb let th (v s = 20v). . . . . . . . . 73.9 mev?cm 2 /mg - total dose, high dose rate . . . . . . . . . . . . . . . 300krad(si) - total dose, low dose rate . . . . . . . . . . . . . . . 100krad(si) * * product capability established by initial characterization. the eh version is acceptance tested on a wafer by wafer basis to 50krad(si) at low dose rate. figure 1. typical application figure 2. v os shift vs high dose rate radiation - + output v + r 1 v - r 2 c 1 c 2 sallen-key low pass filter (f c = 10khz) v in 1.84k 4.93k 3.3nf 8.2nf isl70417seh 0 50 100 150 200 250 300 krad(si) -8 -6 -4 -2 0 2 4 6 v os (v) gnd bias v s = 15v july 2, 2012 fn7962.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl70417seh 2 july 2, 2012 fn7962.0 ordering information ordering number part number (notes 2, 3) temperature range (c) package (pb-free) pkg. dwg. # 5962r1222801vxc isl70417sehvf -55 to +125 14 ld flatpack k14.a isl70417sehf/proto isl70417sehf/proto -55 to +125 14 ld flatpack k14.a 5962r1222801v9ax isl70417sehvx -55 to +125 die isl70417sehx/sample isl70417 sehx/sample -55 to +125 die ISL70417SEHEVAL1Z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for isl70417seh . for more information on msl please see tech brief tb363 .
isl70417seh 3 july 2, 2012 fn7962.0 pin configuration isl70417seh (14 ld flatpack) top view pin descriptions isl70417seh (14 ld flatpack) pin name equivalent circuit description 1 out_a circuit 2 amplifier a output 2 -in_a circuit 1 amplifier a inverting input 3 +in_a circuit 1 amplifier a non-inverting input 4 v+ circuit 3 positive power supply 5 +in_b circuit 1 amplifier b non-inverting input 6 -in_b circuit 1 amplifier b inverting input 7 out_b circuit 2 amplifier b output 8 out_c circuit 2 amplifier c output 9 -in_c circuit 1 amplifier c inverting input 10 +in_c circuit 1 amplifier c non-inverting input 11 v- circuit 3 negative power supply 12 +in_d circuit 1 amplifier d non-inverting input 13 -in_d circuit 1 amplifier d inverting input 14 out_d circuit 2 amplifier d output -+ - + -+ - + bc ad out_a -in_a +in_a v + 1 2 3 4 5 6 7 10 9 8 11 12 13 14 +in_b -in_b out_b v - +in_c -in_c out_c out_d -in_d +in_d circuit 2 circuit 1 v+ v- circuit 3 capacitively coupled esd clamp in- v+ v- in+ 500 ? 500 ? v+ v- out
isl70417seh 4 july 2, 2012 fn7962.0 absolute maximum rating s thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....42v maximum supply voltage (let = 73.9 mev ? cm 2 /mg). . . . . . . . . . . ....40v maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v min/max input voltage . . . . . . . . . . . . . . . . . . . . . . . . v- - 0.5v to v+ + 0.5v max/min input current for input voltage >v+ or isl70417seh 5 july 2, 2012 fn7962.0 i s supply current/amplifier 0.44 0.53 ma 0.68 ma i sc short-circuit current 43 ma v supply supply voltage range guaranteed by psrr 2.25 20 v ac specifications gbwp gain bandwidth product a v = 1k, r l = 2k 1.5 mhz e nvp-p voltage noise v p-p 0.1hz to 10hz 0.25 v p-p e n voltage noise density f = 10hz 10 nv/ hz e n voltage noise density f = 100hz 8.2 nv/ hz e n voltage noise density f = 1khz 8 nv/ hz e n voltage noise density f = 10khz 8 nv/ hz in current noise density f = 1khz 0.1 pa/ hz thd + n total harmonic distortion 1khz, g = 1, v o = 3.5v rms , r l = 2k 0.0009 % 1khz, g = 1, v o = 3.5v rms , r l = 10k 0.0005 % transient response sr slew rate, v out 20% to 80% a v = 11, r l = 2k , v o = 4v p-p 0.3 0.5 v/s 0.2 v/s t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 50mv p-p , r l = 10k to v cm 130 450 ns 625 ns fall time 90% to 10% of v out a v = 1, v out = 50mv p-p , r l = 10k to v cm 130 600 ns 700 ns t s settling time to 0.1% 10v step; 10% to v out a v = -1, v out = 10v p-p , r l = 5k to v cm 21 s settling time to 0.01% 10v step; 10% to v out a v = -1, v out = 10v p-p , r l = 5k to v cm 24 s settling time to 0.1% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k to v cm 13 s settling time to 0.01% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k to v cm 18 s t ol output positive overload recovery time a v = -100, v in = 0.2 v p-p, r l = 2k to v cm 5.6 s output negative overload recovery time a v = -100, v in = 0.2 v p-p, r l = 2k to v cm 10.6 s os+ positive overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 15 % 33 % os- negative overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 15 % 33 % electrical specifications v s 15v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure at a high dose rate of 50 - 300krad (si)/s; and over a total ionizing dose of 50krad(si) with exposure a low dose rate of <10mrad(si)/s. (continued) parameter description conditions min (note 5) typ max (note 5) unit
isl70417seh 6 july 2, 2012 fn7962.0 electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted . boldface limits apply over the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure at a high dose rate of 50 - 300krad (si)/s; and over a total ionizing dose of 50krad(si) with exposu re a low dose rate of <10mrad(si)/s. parameter description conditions min (note 5) typ max (note 5) unit v os input offset voltage 10 150 v 250 v tcv os offset voltage drift 0.1 1 v/ c i b input bias current -1 0.18 1 na -5 5 na tci b input bias current temperature coefficient -5 1 5 pa/c i os input offset current -1.5 0.3 1.5 na -3 3 na tci os input offset current temperature coefficient -3 0.42 3 pa/c v cm input voltage range -3 3 v cmrr common-mode rejection ratio v cm = -3v to +3v 120 145 db 120 db psrr power supply rejection ratio v s = 2.25v to 5v 120 145 db 120 db a vol open-loop gain v o = -3.0v to +3.0v r l = 10k to ground 3,000 14,000 v/mv v oh output voltage high r l = 10k to ground 3.5 3.7 v 3.2 v r l = 2k to ground 3.3 3.55 v 3.0 v v ol output voltage low r l = 10k to ground -3.7 -3.5 v -3.2 v r l = 2k to ground -3.55 -3.3 v -3.0 v i s supply current/amplifier 0.44 0.53 ma 0.68 ma i sc short-circuit current 43 ma ac specifications gbwp gain bandwidth product a v = 1k, r l = 2k 1.5 mhz e np-p voltage noise 0.1hz to 10hz 0.25 v p-p e n voltage noise density f = 10hz 12 nv/ hz e n voltage noise density f = 100hz 8.6 nv/ hz e n voltage noise density f = 1khz 8 nv/ hz e n voltage noise density f = 10khz 8 nv/ hz in current noise density f = 1khz 0.1 pa/ hz transient response sr slew rate, v out 20% to 80% a v = 11, r l = 2k , v o = 4v p-p 0.5 v/s
isl70417seh 7 july 2, 2012 fn7962.0 t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 50mv p-p , r l = 10k to v cm 130 ns fall time 90% to 10% of v out a v = 1, v out = 50mv p-p , r l = 10k to v cm 130 ns t s settling time to 0.1% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k to v cm 12 s settling time to 0.01% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k to v cm 19 s t ol output positive overload recovery time a v = -100, v in = 0.2v p-p r l = 2k to v cm 7s output negative overload recovery time a v = -100, v in = 0.2v p-p r l = 2k to v cm 5.8 s os+ positive overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 15 % os- negative overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 15 % note: 5. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted . boldface limits apply over the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure at a high dose rate of 50 - 300krad (si)/s; and over a total ionizing dose of 50krad(si) with exposure a low dose rate of <10mrad(si)/s. (continued) parameter description conditions min (note 5) typ max (note 5) unit
isl70417seh 8 july 2, 2012 fn7962.0 typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. figure 3. v os vs temperature figure 4. v os vs temperature figure 5. i b + vs temperature figure 6. i b - vs temperature figure 7. i b + vs temperature figure 8. i b - vs temperature temperature (c) v os (v) -100 -50 0 50 100 -75 -50 -25 0 25 50 75 100 125 150 v s = 15v temperature (c) v os (v) -100 -50 0 50 100 -75 -50 -25 0 25 50 75 100 125 150 v s = 5v temperature (c) -75 -50 -25 0 25 50 75 100 125 150 -500 -400 -300 -200 -100 0 100 200 300 400 500 i b+ (pa) v s = 15v temperature (c) -75 -50 -25 0 25 50 75 100 125 150 -500 -400 -300 -200 -100 0 100 200 300 400 500 i b- (pa) v s = 15v temperature (c) -75 -50 -25 0 25 50 75 100 125 150 -500 -400 -300 -200 -100 0 100 200 300 400 500 i b+ (pa) v s = 5v temperature (c) -75 -50 -25 0 25 50 75 100 125 150 -500 -400 -300 -200 -100 0 100 200 300 400 500 i b- (pa) v s = 5v
isl70417seh 9 july 2, 2012 fn7962.0 figure 9. i os vs temperature figure 10. i os vs temperature figure 11. supply current per am p vs temperature figure 12. av ol vs temperature figure 13. psrr vs temperature figure 14. cmrr vs temperature typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) temperature (c) -75 -50 -25 0 25 50 75 100 125 150 -500 -400 -300 -200 -100 0 100 200 300 400 500 i os (pa) v s = 15v temperature (c) -75 -50 -25 0 25 50 75 100 125 150 -500 -400 -300 -200 -100 0 100 200 300 400 500 i os (pa) v s = 5v temperature (c) isupply (ma) 0.2 0.3 0.4 0.5 0.6 0.7 -70 -50 -30 -10 10 30 50 70 90 110 130 vs=15v vs=5v vs=2.25v temperature (c) -75 -50 -25 0 25 50 75 100 125 150 av ol (v/mv) 10000 15000 20000 25000 v o = 13v temperature (c) psrr (db) -70 -50 -30 -10 10 30 50 70 90 110 130 v s = 2.25v to 20v -145 -140 -135 temperature (c) -75 -50 -25 0 25 50 75 100 125 150 cmrr (db) -160 -155 -150 -145 -140 -135 -130 v cm = 13v
isl70417seh 10 july 2, 2012 fn7962.0 figure 15. short circuit current vs temperature figure 16. short circuit current vs temperature figure 17. input v os vs input common mode voltage, v s = 15 figure 18. input v os vs input common mode voltage, v s = 5v figure 19. v out vs temperature figure 20. v out vs temperature typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) temperature (c) i sc + (ma) 30 35 40 45 50 55 60 65 70 75 80 -70 -50 -30 -10 10 30 50 70 90 110 130 i sc + @ 15v temperature (c) i sc- (ma) 30 35 40 45 50 55 60 65 70 75 80 -70 -50 -30 -10 10 30 50 70 90 110 130 i sc - @ 15v -60 -40 -20 0 20 40 60 80 100 -15 -10 -5 0 5 10 15 vcm (v) v os (v) v s = 15v +125c +25c -55c -60 -40 -20 0 20 40 60 80 100 -5 -3 -1 1 3 5 v cm (v) v os (v) v s = +5v +125c +25c -55c temperature (c) -70 -50 -30 -10 10 30 50 70 90 110 130 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14.0 14.1 14.2 v oh (v) v s = +15v r l = 10k ? temperature (c) -70 -50 -30 -10 10 30 50 70 90 110 130 v ol (v) -14 .2 -14.1 -14.0 -13.9 -13.8 -13.7 -13.6 -13.5 -13.4 -13.3 -13.2 -13.1 v s = +15v r l = 10k ?
isl70417seh 11 july 2, 2012 fn7962.0 figure 21. v out vs temperature figure 22. v out vs temperature figure 23. input noise voltage 0.1hz to 10hz figu re 24. input noise voltage spectral density figure 25. input noise current sp ectral density figure 26. open-loop gain, phase vs frequency, r l =10k , c l = 10pf typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) temperature (c) -70 -50 -30 -10 10 30 50 70 90 110 130 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14.0 14.1 14.2 v oh (v) v s = +15v r l = 2k ? temperature (c) -70 -50 -30 -10 10 30 50 70 90 110 130 v ol (v) -14 .2 -14.1 -14.0 -13.9 -13.8 -13.7 -13.6 -13.5 -13.4 -13.3 -13.2 -13.1 v s = +15v r l = 2k ? time (s) input noise voltage (nv) 012345678910 -250 -200 -150 -100 -50 0 50 100 150 200 250 v+ = 36.4v r g = 10, r f = 100k av = 10,000 frequency (hz) 1 10 100 1 10 100 1k 10k 100k input noise voltage (nv/?hz) v s = 18.2v av = 1 frequency (hz) 1 10 100 1k 10k 100k 1 input noise current (pa/?hz) 0.1 v s = 18.2v av = 1 open loop gain (db)/phase () frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 10pf gain phase
isl70417seh 12 july 2, 2012 fn7962.0 figure 27. open-loop gain, phase vs frequency, r l =10k , c l = 100pf figure 28. cmrr vs frequency, v s = 2.25, 5v, 15v figure 29. psrr vs frequency, v s = 5v, 15v figure 30. frequency response vs closed loop gain figure 31. frequency response vs feedback resistance r f /r g figure 32. gain vs frequency vs r l typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) open loop gain (db)/phase () frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 100pf gain phase cmrr (db) frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = inf simulation c l = 10pf v s = 2.5v v s = 5v v s = 15v 0 psrr (db) 100 1k 10k 100k 1m 10m frequency (hz) 10 20 40 60 80 100 120 -10 10 30 50 70 90 110 r l = inf av = +1 v cm = 1v p-p c l = 4pf psrr+ and psrr- v s = 15v psrr+ and psrr- v s = 2.25v frequency (hz) gain (db) 100k 1m 10m 10 10k 1k -10 0 10 20 30 40 50 60 70 100 av = 1 av = 100 av = 1000 v s = 20v v out = 50mv p-p c l = 4pf r l = 10k r g = 10k, r f = 100k av = 10 r g = 1k, r f = 100k r g = open, r f = 0 r g = 100, r f = 100k normalized gain (db) -10 -8 -6 -4 -2 0 2 4 -16 -14 -12 frequency (hz) 100k 1m 10m 10 10k 1k 100 r f = r g = 100k r f = r g = 100 r f = r g = 10k r f = r g = 1k v s = 20v r l = 10k av = +2 v out = 50mv p-p c l = 4pf frequency (hz) 100k 1m 10m 10 10k 1k 100 gain (db) -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 v s = 20v av = +1 v out = 50mv p-p c l = 4pf r l = 499 r l = 100 r l = 4.99k r l = 10k r l = 1k
isl70417seh 13 july 2, 2012 fn7962.0 figure 33. gain vs frequency vs c l figure 34. gain vs frequency vs supply voltage figure 35. crosstalk, v s = 15v figure 36. large signal transient response vs r l v s = 5v, 15v figure 37. slew rate vs temperature v s = 5v, 15v figure 38. small signal transient response, v s = 5v, 15v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) frequency (hz) 100k 1m 10m 10 10k 1k 100 gain (db) -8 -6 -4 -2 0 2 4 6 8 10 12 v s = 2.5v r l = 10k av = +1 v out = 50mv p-p c l = 0.01f c l = 270pf c l = 47pf c l = 1000pf c l = 470pf c l = 4pf c l = 100pf frequency (hz) 100k 1m 10m 10 10k 1k 100 gain (db) -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 c l = 4pf r l = 10k av = +1 v out = 50mv p-p v s = 5v v s = 20v v s = 2.25v v s = 15v 0 20 40 60 80 100 120 140 160 180 10 100 1k 10k 100k 1m 10m frequency (hz) crosstalk (db) v s = 15v r l -driver ch. = open av = +1 v source = 1v p-p c l = 4pf r l -receiving ch. = 10k time (s) large signal t ransient r esponse (v) -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 0 102030405060708090100 av = +1 cl = 4pf v out = 4v p-p v s = 5v, rl = 2k, 10k v s = 15v, rl = 2k, 10k temperature (c) -70 -50 -30 -10 10 30 50 70 90 110 130 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 slew rate (v/us) sr+ sr- r l = 2k, 10k av = 1 c l = 7pf v out = 4v p-p v s = 5v, 15v time (s) small signal t ransient r esponse (mv) -10 0 10 20 30 40 50 60 0 5 10 15 20 25 30 35 40 rl = 10k av = +1 cl = 4pf v out = 50mv p-p v s =5, 15v
isl70417seh 14 july 2, 2012 fn7962.0 figure 39. positive output overload response time, v s = 5v, 15v figure 40. negative output overload response time, v s = 5v, 15v figure 41. % overshoot vs load capacitance, v s = 15v figure 42. output phase reversal response vs temperature typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) time (s) output voltage (v) input voltage (v) -0.28 -0.24 -0.20 -0.16 -0.12 -0.08 -0.04 0.04 0 102030405060708090100 -2 0 2 4 6 8 10 12 14 0 input output @ vs = 15v r l = 2k av = -100 c l = 4pf r f = 100k, r g = 1k v in = 200mv p-p output @ v s = 5v time (s) output voltage (v) input voltage (v) 0 102030405060708090100 -0.08 -0.04 0 0.04 0.08 0.12 0.16 0.20 0.24 -12 -10 -8 -6 -4 -2 0 2 4 input output @ v s = 15v r l = 2k av = -100 c l = 4pf r f = 100k, r g = 1k v in = 200mv p-p output @ v s = 5v capacitance (pf) 0 10 20 30 40 50 60 70 80 10 100 1k 10k overshoot (%) 1 o v e r s h o o t + v s = 15v r l = 10k av = 1 v out = 50mv p-p o v e r s h o o t - 100k -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 0.2 1 1.2 1.4 1.6 1.8 2 v in and v out (v) time(ms) 0.4 0.6 0.8 r l = 10k av = 1 c l = 7pf v in = 5.9v p-p v s = 5v vin vout @ 25 c vout @ -55 c vout @ 125 c
isl70417seh 15 july 2, 2012 fn7962.0 post high dose radiation characteristics unless otherwise specified, v s 15v, v cm = 0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposu re at a high dose rate of 50 - 300rad(si)/s. this data is intended to show typical parameter shifts due to high dose rate radiation. these are not limits nor are they guaranteed figure 43. supply current per amp vs high dose rate radiation figure 44. v os vs high dose rate radiation figure 45. i b + vs high dose rate radiation figure 46. i b - vs high dose rate radiation figure 47. i os vs high dose rate radiation 0.440 0.442 0.444 0.446 0.448 0.450 0.452 0.454 0.456 0.458 0.460 0 50 100 150 200 250 300 krad(si) isupply (ma) gnd bias 0 50 100 150 200 250 300 krad(si) -8 -6 -4 -2 0 2 4 6 v os (v) gnd bias 0 50 100 150 200 250 300 krad(si) 0 100 200 300 400 500 600 700 800 900 1000 i b+ (pa) gnd bias 0 50 100 150 200 250 300 krad(si) i b- (pa) -400 -300 -200 -100 0 100 200 300 400 500 gnd bias 0 50 100 150 200 250 300 krad(si) -400 -350 -300 -250 -200 -150 -100 -50 0 gnd bias i os (pa)
isl70417seh 16 july 2, 2012 fn7962.0 post low dose radiation characteristics unless otherwise specified, v s 15v, v cm = 0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical param eter shifts due to low dose rate radiation. these are not limits nor are they guaranteed figure 48. supply current per amp vs low dose rate radiation figure 49. v os vs low dose rate radiation figure 50. i b + vs low dose rate radiation figure 51. i b - vs low dose rate radiation figure 52. i os vs low dose rate radiation krad(si) isupply (ma) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 20406080100 gnd bias krad(si) v os (v) -110 -90 -70 -50 -30 -10 10 30 50 70 90 110 0 102030405060708090100 gnd bias krad(si) i b+ (pa) -5 -4 -3 -2 -1 0 1 2 3 4 5 0 20406080100 gnd bias krad(si) i b- (pa) -5 -4 -3 -2 -1 0 1 2 3 4 5 0 20406080100 bias gnd krad(si) i os (pa) -3 -2 -1 0 1 2 3 bias gnd 0 20406080100
isl70417seh 17 july 2, 2012 fn7962.0 applications information functional description the isl70417seh contains four, low noise precision op amps. these devices are fabricated in a new precision 40v complementary bipolar di process. a super-beta npn input stage with input bias current cancella tion provides low input bias current (180pa typical), low inpu t offset voltage (13v typical), low input noise voltage (8nv/ hz), and low 1/f noise corner frequency (~8hz). these amplifiers also feature high open loop gain (14kv/mv) for excellent cmrr (145db) and thd+n performance (0.0005% @ 3.5v rms , 1khz into 2k ). a complementary bipolar output st age enables high capacitive load drive without external compensation. operating voltage range the devices are designed to operate over the 4.5v (2.25v) to 40v (20v) voltage range and are fully characterized at 10v (5v) and 30v (15v). the power supply rejection ratio typically exceeds 140db over the full operating voltage range and 120db minimum over the -55c to +1 25c temperature range. the worst case common mode input voltage range over temperature is 2v to each rail. with 15v supplies, cmrr performance is typically >130db over-tempe rature. the minimum cmrr performance over the -55c to +125c temperature range is >120db for power supply voltages from 5v (10v) to 15v (30v). input performance the super-beta npn input pair provides excellent frequency response while maintaining high input precision. high npn beta (>1000) reduces input bias current while maintaining good frequency response, low input bias current and low noise. input bias cancellation circuits pr ovide additional bias current reduction to <5na, and excellent temperature stabilization. figures 6 through 8 show the high degree of bias current stability at 5v and 15v supplies that is maintained across the -55c to +125c temperature range. the low bias current tc also produces very low input offset current tc, which reduces dc input offset errors in precision, high impedance amplifiers. the +25c maximum input offset voltage (v os ) is 75v at 15v supplies. input offset voltage temperature coefficients (v os tc) is a maximum of 1.0v/c. the v os temperature behavior is smooth (figures 3 through 4) maintaining constant tc across the entire temperature range. input esd diode protection the input terminals (in+ and in-) have internal esd protection diodes to the positive and negative supply rails, series connected 500 current limiting resistors and an anti-parallel diode pair across the inputs (figure 53). the series resistors limit the high feed-through currents that can occur in pulse applications wh en the input dv/dt exceeds the 0.5v/s slew rate of the amplifier. without the series resistors, the input can forward-bias the anti-par allel diodes causing current to flow to the output resulting in severe distortion and possible diode failure. figure 36 provides an example of distortion free large signal response using a 4v p-p input pulse with an in put rise time of <1ns. the series resistors enable the input differential voltage to be equal to the maximum power supply voltage (40v) without damage. in applications where one or both amplifier input terminals are at risk of exposure to high voltages beyond the power supply rails, current limiting resistors may be needed at the input terminal to limit the current through the power supply esd diodes to 20ma max. output current limiting the output current is internally limited to approximately 45ma at +25c and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. this applies to only 1 amplifier at a time for the quad op amp. continuous operation under these conditio ns may degrade long term reliability. figures 15 and 16 show the current limit variation with temperature. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl70417seh is immune to output phase reversal, even when the input voltage is 1v beyond the supplies. power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to ca lculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) figure 53. input esd diode current limiti ng- unity gain - + r l v in v out v+ v- 500 500 t jmax t max ja xpd maxtotal + = (eq. 1)
isl70417seh 18 july 2, 2012 fn7962.0 ?pd max for each amplifier can be calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipa tion of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application pd max v s i qmax v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2)
isl70417seh 19 july 2, 2012 fn7962.0 package characteristics weight of packaged device 0. 6043 grams (typical) lid characteristics finish: gold potential: unbiased case isolation to any lead: 20 x 10 9 ? (min) die characteristics die dimensions 2028m x 2568m (80mils x 101mils) thickness: 483m 25m (19mils 1 mil) interface materials glassivation type: nitrox thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon process dielectrically isolated complementary bipolar - pr40 assembly related information substrate potential floating additional information worst case current density < 2 x 10 5 a/cm 2 metallization mask layout place holder v+ out_c -in_c +in_c v- +in_a -in_a out_a out_d -in_d +in_d out_b -in_b +in_b
isl70417seh 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com july 2, 2012 fn7962.0 for additional products, see www.intersil.com/product_tree table 1. die layout x-y coordinates pad name pad number x (m) y (m) dx (m) dy (m) bond wires per pad out_a 3 -256 1152 70 70 1 -in_a 4 -661 1152 70 70 1 +in_a 5 -867.5 948.5 70 70 1 v+ 9 -880.5 0 70 70 1 +in_b 13 -867.5 -948.5 70 70 1 -in_b 14 -661 -1152 70 70 1 out_b 15 -256 -1152 70 70 1 out_c 16 256 -1152 70 70 1 -in_c 17 661 -1152 70 70 1 +in_c 18 867.5 -948.5 70 70 1 v- 22 880.5 0 70 70 1 +in_d 26 867.5 948.5 70 70 1 -in_d 1 661 1152 70 70 1 out_d 2 256 1152 70 70 1 note: 6. origin of coordinates is the center of die.
isl70417seh 21 july 2, 2012 fn7962.0 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl70417seh to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 2, 2012 fn7962.0 initial release
isl70417seh 22 july 2, 2012 fn7962.0 package outline drawing ceramic metal seal flat pack packages (flatpack) notes: 1. index area: a notch or a pin one iden tification mark shall be located ad- jacent to pin one and shall be locat ed within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identi- fication mark. alternately, a tab (dim ension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-cen ter lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m ap- plies to lead plating and finish th ickness. the maximum limits of lead dimensions b and c or m shall be m easured at the centroid of the fin- ished lead surfaces, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the menis- cus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and toleranc ing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k14.a mil-std-1835 cdfp3-f14 (f -2a, configuration b) 14 lead ceramic metal se al flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.390 - 9.91 3 e 0.235 0.260 5.97 6.60 - e1 -0.290 -7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.270 0.370 6.86 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n14 14- rev. 0 5/18/94

▲Up To Search▲

Price & Availability of ISL70417SEHEVAL1Z

	To Download ISL70417SEHEVAL1Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .